Field of the Invention
The following description relates to a display device, and, for example, to a column data driver configured to apply a voltage or current corresponding to image data to a display panel, a display device having the column data driver, and a driving method of the display device.
Description of Related Art
In general, a liquid crystal display device (LCD), which is one of display devices, displays an image by controlling the light transmittance of liquid molecules with dielectric anisotropy using an electric field. To this end, the LCD includes a liquid crystal panel provided with a plurality of pixels arranged in a matrix form, and a driving circuit configured to drive the liquid crystal panel.
The liquid crystal panel includes a plurality of gate lines (hereinafter, referred to as ‘row lines’) and a plurality of column lines (hereinafter, referred to as ‘column lines’) crossing the plurality of gate lines. The pixels are arranged in regions where the row lines and the column lines cross each other. Pixel electrodes and a common electrode are formed so as to apply an electric field to each of the pixels. Each of the pixels contacts a switching element, e.g., a thin film transistor (hereinafter, referred to as TFT).
The driving circuit includes a row data driver configured to drive the row lines, a column data driver configured to drive the column lines, a timing controller configured to supply a control signal used to control the row data driver and the column data driver, and a common electrode voltage generator configured to supply a common electrode voltage to the liquid crystal panel.
FIG. 1 is a block diagram of an LCD including a conventional column data driver. FIG. 1 exemplarily illustrates a liquid crystal panel having 2×3 configuration in an M-by-N matrix (M and N are positive integers).
Referring to FIG. 1, the conventional LCD includes a liquid crystal panel 110, a row data driver 120, a column data driver 130, and a timing controller (not shown).
The liquid crystal panel 110 includes a plurality of row lines RL1 to RLm, a plurality of column lines CL1 to CLn, and a plurality of pixels Px arranged in regions where the row lines RL1 to RLm and the column lines CL1 to CLn cross each other. The pixel Px includes a switch 112 and a liquid crystal 111.
The row data driver 120 controls the switch 112 of each pixel in a row direction of the liquid crystal panel 110. To be specific, the row data driver 120 sequentially outputs scan pulses to the switch 112 in response to a gate control signal supplied from the timing controller.
The column data driver 130 outputs a data signal corresponding to image data input in response to a data control signal of the timing controller, to the column lines CL1 to CLn.
The column data driver 130 includes a digital-to-analog converter (DAC) 133, buffers 132_1 to 132_3, and column switches SW1 to SW3. The DAC 133 receives the image data to convert them into analog signals. The buffers 132_1 to 132_3 receive the respective analog signals (data signals) output from the DAC 133 to drive column lines of the liquid crystal panel 110. The column switches SW1 to SW3 transfer the data signals buffered through the buffers 132_1 to 132_3 to the corresponding column lines CL1 to CLn, respectively.
FIG. 2 is an operation waveform diagram illustrating the operation of the LCD of FIG. 1.
Referring to FIG. 2, the column switches SW1 to SW3 are simultaneously turned on or off in general. The row lines RL1 to RLm transfer the scan pulses to the switches 112 in sequence. A voltage or current corresponding to the data signal is applied to the column lines CL1 to CLn when the column switches SW1 to SW3 are turned on. At this time, there is a slewing due to a time delay (RC delay) of the pixel. The slewing is a critical factor to charge the pixel. When the slewing is too slow, it is difficult to display an image correctly.
FIG. 3 is a block diagram of another conventional LCD. Number of buffers in a column data driver of the conventional LCD of FIG. 3 is reduced compared to the conventional LCD of FIG. 1.
Referring to FIG. 3, a column data driver 140 includes a DAC 143, a buffer 142, and a plurality of column switches SW1 to SW3. The plurality of column switches SW1 to SW3 are connected to one buffer 142. Accordingly, to transfer the data signal output from the buffer 142 to a plurality of column lines CL1 to CL3 correspondingly, the data signal of the buffer 142 is sequentially transferred to the column lines CL1 to CL3 through the column switches SW1 to SW3 while the row line RL1 is enabled. Such an operating method is called a time-sharing method.
FIG. 4 is an operation waveform diagram of the LCD of FIG. 3, illustrating a time-sharing method. A solid line in the waveform diagram of each of the column lines CL1 to CL3 denotes a duration during which a data signal is actually output from the buffer of the column data driver, whereas a dotted line denotes a duration during which the data signal of the buffer is in a floating state because each column switch SW1 to SW3 is turned off.
As illustrated in FIG. 4, a time-sharing operation should be performed using the column switches SW1 to SW3 during the activation of the same row line, e.g., RL1 or RL2, in the conventional LCD of FIG. 3 employing the time-sharing method. Therefore, a slew margin of the buffer 142 becomes poorer compared to the conventional LCD of FIG. 1.
While number (k) of buffers, i.e., time-sharing channels, in FIG. 3 is 3, it is possible to arbitrarily change the number (k) to, for example, k=2, 6, 12, etc., depending on characteristics of the column data driver and the liquid crystal panel. However, as the number of buffers performing the time-sharing operation becomes greater, a settling time margin of the data signal of the buffer, i.e., a settling time margin of an output voltage or output current gets shorter because the allowed time for settling is in inverse proportion to the number (k).
To solve the above-described limitations, a liquid crystal panel using a low temperature polysilicon (LTPS) technique has been developed to reduce a signal delay time or settling time due to parasitic resistance and capacitance in the liquid crystal panel, which leads to an increase in cost in comparison with existing TFT panels.